An integrated circuit physical design tool includes an interconnection congestion predictor that generates a congestion table for an integrated circuit design. Interconnection congestion hotspots are identified based on the congestion table. The proximity of interconnection congestion hotspots to each other is determined, and penalization values are computed based on the proximity of interconnection congestion hotspots to each other. The congestion table is then updated to reflect the penalization values due to proximity of interconnection congestion hotspots. Routability of the interconnection congestion hotspots is then predicted based on the updated congestion table. The updated congestion table may also be used by multiple physical design optimization tools, including placement, global routing, and detail routing.