Embodiments of the present invention disclose an image chip. The image chip includes: a processor for dividing an image frame into at least two image segments, a read circuit for reading the at least two image segments in a time-division manner, and an image synthesizer for successively performing image synthesis on the at least two image segments according to a time sequence read by the read circuit. The image frame comprises multiple layers and each layer in the multiple layers is a rectangular layer having two first boundaries. Two first boundaries of a first image segment in the at least two image segments correspond to two neighboring boundaries in all the first boundaries of the multiple layers. The image synthesis for each image segment in the at least two image segments comprises image synthesis for all sublayers in the each image segment.