A semiconductor storage device includes first and second memory cell transistors at opposite sides of a first semiconductor body, third and fourth memory cell transistors at opposite sides of a second semiconductor body, a first word line connected to gates of the first and third memory cell transistors, a second word line connected to gates of the second and fourth memory cell transistors, and a controller. During a program operation on the third memory cell transistor, the controller determines a program voltage on the basis of a first number of loops determined during the write operation performed on the first memory cell transistor, and during a program operation on the fourth memory cell transistor, the controller determines a program voltage on the basis of a second number of loops determined during the write operation performed on the second memory cell transistor.