Invention Grant
- Patent Title: Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance
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Application No.: US16276738Application Date: 2019-02-15
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Publication No.: US10832907B2Publication Date: 2020-11-10
- Inventor: Kangguo Cheng , Yi Song , Zhenxing Bi
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Douglas Pearson
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/308 ; H01L29/66 ; H01L29/78 ; H01L29/165 ; H01L29/06 ; H01L29/423 ; H01L29/08

Abstract:
Devices and methods are provided for fabricating field-effect transistors having source/drain extension contacts to provide reduced parasitic resistance in electrical paths between source/drain layers and active channel layers surrounded by gate structures of the field-effect transistor devices. For example, in a nanosheet field-effect transistor device having embedded gate sidewall spacers which are disposed between end portions of active nanosheet channel layers and serve to insulate source/drain layers from a metal gate structure, epitaxial source/drain extension contacts are disposed between the embedded gate sidewall spacers and active nanosheet channel layers, and on sidewall surfaces of the active nanosheet channel layers. Epitaxial source/drain layers are grown starting on exposed surfaces of the epitaxial source/drain extension contacts. The epitaxial source/drain extension contacts laterally extend from epitaxial source/drain layers to a high-k dielectric/metal gate structure that surrounds the active nanosheet channel layers.
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