Invention Grant
- Patent Title: Logic gate designs for 3D monolithic direct stacked VTFET
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Application No.: US16455665Application Date: 2019-06-27
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Publication No.: US10833069B2Publication Date: 2020-11-10
- Inventor: Chen Zhang , Tenko Yamashita , Terence B. Hook
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Randall Bluestone; Michael J. Chang, LLC
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L29/66 ; H01L29/10 ; H01L23/528 ; H01L21/8238 ; H01L21/822 ; H01L29/78 ; H01L29/786 ; H01L27/092 ; H01L29/08 ; H01L21/84 ; H01L21/225 ; H03K19/0948 ; H01L27/12 ; H01L27/02 ; H03K19/21 ; H03K19/20
Abstract:
Logic gate designs (e.g., NAND, NOR, Inverter) for stacked VTFET designs are provided. In one aspect, a logic gate device is provided. The logic gate device includes: at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2); a power rail connected to a power contact of the logic gate device; and a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device. A method of forming a logic gate device is also provided.
Public/Granted literature
- US20190326279A1 Logic Gate Designs for 3D Monolithic Direct Stacked VTFET Public/Granted day:2019-10-24
Information query
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