Invention Grant
- Patent Title: Low resistance contact interlayer for semiconductor devices
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Application No.: US14821330Application Date: 2015-08-07
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Publication No.: US10833187B2Publication Date: 2020-11-10
- Inventor: Jeehwan Kim , Wencong Liu , Devendra K. Sadana
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Erik Johnson
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/267 ; H01L29/66 ; H01L29/08 ; H01L29/45 ; H01L21/441 ; H01L29/861
Abstract:
A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type material includes an oxide of a II-VI material. An oxygen scavenging interlayer is formed on the n-type material. An aluminum contact is formed in direct contact with the oxygen scavenging interlayer to form an electronic device.
Public/Granted literature
- US20170040463A1 LOW RESISTANCE CONTACT INTERLAYER FOR SEMICONDUCTOR DEVICES Public/Granted day:2017-02-09
Information query
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