The present document discloses a circuitry for delaying a digital input signal. In particular, the circuitry may comprise a delay cell circuit and a reciprocal current digital-to-analog converter (DAC). The delay cell circuit may be coupled to the reciprocal current DAC. More particularly, the reciprocal current DAC may be configured to output a charge current to the delay cell circuit according to a value of a control input provided to the reciprocal current DAC. The charge current output by the reciprocal current DAC may be inversely proportional to the value of the control input, wherein the delay depends on the charge current.