High speed radar test system processing and logic
Abstract:
A radar test computing system includes a host interface coupled to a programmable input/output (I/O) controller, which is to interface with propagation path replicator (PPR) circuitry. A processing device is to detect a start signal received from the controller; receive an update request from the controller in response to detection, by the PPR circuitry, of a first radio RF pulse on a RF signal received from the radar system; retrieve scenario data of distance to and speed of the moving target for a second RF pulse expected to follow the first RF pulse; calculate, using retrieved scenario data, values of a frequency shift, a signal delay, and a signal attenuation for the second RF pulse; and send, during a time period between the first and second RF pulses, these values to the controller for use by the PPR circuitry to simulate the moving target for the second RF pulse.
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