Invention Grant
- Patent Title: Mask pattern correction system, and semiconductor device manufacturing method utilizing said correction system
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Application No.: US16566363Application Date: 2019-09-10
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Publication No.: US10852648B2Publication Date: 2020-12-01
- Inventor: Kazuyuki Hino , Hiromitsu Mashita , Masahiro Miyairi , Hiroshi Yoshimura , Taiga Uno , Sachiyo Ito , Shinichirou Ooki , Kenji Shiraishi , Hirotaka Ichikawa , Yuto Takeuchi
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: JP2018-191384 20181010
- Main IPC: G03F7/20
- IPC: G03F7/20 ; G03F1/00 ; G03F1/72 ; G06F30/23 ; G06F30/30

Abstract:
According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.
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Information query
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