Invention Grant
- Patent Title: Host-resident translation layer validity check techniques
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Application No.: US16140952Application Date: 2018-09-25
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Publication No.: US10852964B2Publication Date: 2020-12-01
- Inventor: Nadav Grosz
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/10
Abstract:
Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.
Public/Granted literature
- US20200097194A1 HOST-RESIDENT TRANSLATION LAYER VALIDITY CHECK TECHNIQUES Public/Granted day:2020-03-26
Information query
