A processor including a physical register file with multiple physical registers, mapping logic, and a merge system. The mapping logic maps up to a first maximum number of the physical registers for each architectural register specified in received program instructions and stores corresponding mappings in a rename table. The merge system generates a merge instruction for each architectural register that needs to be merged, inserts each generated merge instruction into the program instructions to provide a modified set of instructions, and that issues the modified set of instructions in consecutive issue cycles based on a take rule. In one embodiment, the first maximum number may be two.