Invention Grant
- Patent Title: Memory controller
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Application No.: US15693275Application Date: 2017-08-31
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Publication No.: US10853234B2Publication Date: 2020-12-01
- Inventor: Sho Kodama
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JP2017-056500 20170322
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F3/06 ; G06F12/06

Abstract:
A memory controller controls first and second memory, and includes a control unit. In response to a first write command from a host, which designates a logical address for first data to be written to the first memory, the control unit determines whether mapping of the logical address is presently being managed in a first mode with a first cluster size or a second mode with a second cluster size that is smaller than the first cluster size, changes first mapping data for the logical address stored in a first table in the second memory, from the first cluster size to the second cluster size, if the mapping of the logical address is being managed in the first mode and the first mapping data can be compressed at a ratio lower than a first compression ratio, and writes the first data to a physical address of the first memory.
Public/Granted literature
- US20180276114A1 MEMORY CONTROLLER Public/Granted day:2018-09-27
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