According to one embodiment, an information processing device includes a processor configured to refer to address conversion data. The address conversion data has a plurality of logical addresses associated with a plurality of physical addresses of a storage device. The processor converts the plurality of logical addresses of an evaluation target in storage device into the corresponding plurality of physical addresses for the evaluation target by referring to the address conversion data. The processor then calculates an evaluation value indicating a parallel reading performance for the plurality of physical addresses of the evaluation target using a parameter specifying a number of areas of the storage device readable in parallel.