Invention Grant
- Patent Title: Methods and apparatuses for addressing memory caches
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Application No.: US16157908Application Date: 2018-10-11
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Publication No.: US10853261B2Publication Date: 2020-12-01
- Inventor: Trung Diep , Hongzhong Zheng
- Applicant: Rambus Inc.
- Applicant Address: US CA San Jose
- Assignee: RAMBUS INC.
- Current Assignee: RAMBUS INC.
- Current Assignee Address: US CA San Jose
- Agency: Morgan, Lewis & Bockius LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/1009 ; G06F12/0864 ; G06F12/0811 ; G11C7/10

Abstract:
A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.
Public/Granted literature
- US20190179768A1 Methods and Apparatuses for Addressing Memory Caches Public/Granted day:2019-06-13
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