Improving an initial via in a circuit comprises: obtaining layout information associated with an initial via structure in a circuit, the initial via comprising an initial lower metal enclosure and an initial upper metal enclosure connected by an initial cut; determining layout information associated with a multiconnection via structure comprising a plurality of sibling vias having at least one additional upper metal enclosure and at least one additional lower metal enclosure; updating the layout information associated with the initial via with the layout information associated with the multiconnection via structure; and outputting the updated layout information. The plurality of sibling vias are connected by a plurality of corresponding sibling cuts, and the multiconnection via structure has lower resistance than the initial via structure. In some embodiments, the multiconnection via is efficiently represented in using a master template.