Invention Grant
- Patent Title: Memory with high-speed and area-efficient read path
-
Application No.: US16421365Application Date: 2019-05-23
-
Publication No.: US10854246B1Publication Date: 2020-12-01
- Inventor: Adithya Bhaskaran , Mukund Narasimhan , Shiba Narayan Mohanty
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Haynes and Boone, LLP
- Main IPC: G11C7/06
- IPC: G11C7/06 ; G11C7/10 ; H03K19/20
Abstract:
A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.
Public/Granted literature
- US20200372939A1 Memory with High-Speed and Area-Efficient Read Path Public/Granted day:2020-11-26
Information query
