Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers a arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.