Invention Grant
- Patent Title: Method and structure for semiconductor device having gate spacer protection layer
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Application No.: US16118744Application Date: 2018-08-31
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Publication No.: US10854458B2Publication Date: 2020-12-01
- Inventor: Chih Wei Lu , Chung-Ju Lee , Hai-Ching Chen , Chien-Hua Huang , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/768 ; H01L29/49 ; H01L23/485 ; H01L29/78

Abstract:
A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
Public/Granted literature
- US20180374708A1 Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer Public/Granted day:2018-12-27
Information query
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