Invention Grant
- Patent Title: Manufacturing method of a semiconductor device and method for creating a layout thereof
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Application No.: US16601066Application Date: 2019-10-14
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Publication No.: US10854546B2Publication Date: 2020-12-01
- Inventor: Kosuke Yanagidaira , Chikaaki Kodama
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-320444 20071212
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/311 ; H01L21/768 ; H01L23/522 ; H01L27/11519 ; H01L27/11526 ; H01L27/11529 ; H01L27/02 ; H01L23/48

Abstract:
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
Public/Granted literature
- US20200043845A1 MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF Public/Granted day:2020-02-06
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