Invention Grant
- Patent Title: Method of manufacturing mark
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Application No.: US16575395Application Date: 2019-09-19
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Publication No.: US10854555B1Publication Date: 2020-12-01
- Inventor: Hsiao-Chiang Lin , Chia-Kuang Lee , Shih-Ci Yen
- Applicant: Powerchip Semiconductor Manufacturing Corporation
- Applicant Address: TW Hsinchu
- Assignee: Powerchip Semiconductor Manufacturing Corporation
- Current Assignee: Powerchip Semiconductor Manufacturing Corporation
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Priority: TW108123773A 20190705
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L23/544 ; H01L21/768
Abstract:
A method of manufacturing a mark including the following steps is provided. A substrate including a device area and a mark area is provided. A dielectric layer is formed on the substrate. A dual damascene opening is formed in the dielectric layer of the device area. The dual damascene opening includes a first opening and a second opening connected to each other. The width of the second opening is greater than the width of the first opening. A third opening is formed in the dielectric layer of the mark area. The third opening and the first opening are simultaneously formed by the same process. A barrier material layer is formed on the surfaces of the dual damascene opening and the third opening. The barrier material layer seals the third opening to form a void in the third opening. A metal material layer is formed on the barrier material layer.
Information query
IPC分类:
