Invention Grant
- Patent Title: Three-dimensional memory device containing a capped insulating source line core and method of making the same
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Application No.: US16023035Application Date: 2018-06-29
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Publication No.: US10854627B1Publication Date: 2020-12-01
- Inventor: Takumi Moriyama , Satoshi Shimizu , Kiyohiko Sakakibara
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11524 ; H01L21/762 ; H01L27/1157 ; H01L29/06 ; H01L27/11556

Abstract:
In-process source-level material layers including a source-level sacrificial layer are formed over a substrate, and an alternating stack of insulating layers and spacer material layers and memory stack structures are formed over the in-process source-level layers. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer employing an etchant provided through the backside trench. A source contact layer including a doped semiconductor material is formed on vertical semiconductor channels of the memory stack structures within the source cavity. The source contact layer includes an unfilled cavity, which is subsequently filled with a silicon nitride liner, a silicon oxide fill material and a semiconductor cap. A semiconductor oxide structure can be formed by filling voids in the silicon oxide fill material by oxidizing the semiconductor cap into a thermal semiconductor oxide material portion.
Information query
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