Invention Grant
- Patent Title: Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
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Application No.: US16192923Application Date: 2018-11-16
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Publication No.: US10854717B2Publication Date: 2020-12-01
- Inventor: Hideki Takeuchi , Daniel Connelly , Marek Hytha , Richard Burton , Robert J. Mears
- Applicant: ATOMERA INCORPORATED
- Applicant Address: US CA Los Gatos
- Assignee: ATOMERA INCORPORATED
- Current Assignee: ATOMERA INCORPORATED
- Current Assignee Address: US CA Los Gatos
- Agency: Allen, Dyer, Doppelt + Gilchrist, P.A.
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L29/08 ; H01L29/66 ; H01L21/225 ; H01L21/283 ; H01L29/78 ; H01L29/45 ; H01L21/265

Abstract:
A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
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