Invention Grant
- Patent Title: Tiered error correction code (ECC) operations in memory
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Application No.: US16424836Application Date: 2019-05-29
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Publication No.: US10860416B2Publication Date: 2020-12-08
- Inventor: Mustafa N. Kaynak , Patrick R. Khayat , Sivagnanam Parthasarathy
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10 ; H03M13/29 ; H03M13/37 ; H03M13/11 ; H03M13/15 ; H03M13/00
Abstract:
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.
Public/Granted literature
- US20190278654A1 TIERED ERROR CORRECTION CODE (ECC) OPERATIONS IN MEMORY Public/Granted day:2019-09-12
Information query
