A memory system may include: a multi-level cell memory device; and a controller suitable for controlling the memory device, wherein the controller includes a processor suitable for searching for the last programmed word line in an open memory block when the memory system is powered up after a sudden power-off, and controlling sequential read operations on data of the memory device in a plurality of logical pages corresponding to the last programmed word line, wherein the processor ends the sequential read operations depending on whether error correction on sequentially read data fails, receives from a host the error correction-failed data and data on which the sequential read operations are not performed, and controls the memory device to program the received data.