The present invention discloses a counting circuit of a performance monitor unit, capable of preventing a cycle counter from being suspended due to the occurrence of an overflow. An embodiment of the counting circuit includes a cycle counter and an event counter. The cycle counter starts counting from a beginning number according to a cycle of a clock signal during enablement duration, and when a count of the cycle counter reaches a count maximum of the cycle counter during the enablement duration, the cycle counter changes a level of a trigger signal and then counts from the beginning number again. The event counter counts according to change of the level of the trigger signal. Accordingly, the counting circuit is operable to obtain a total cycle number of the clock signal in the enablement duration according to the count of the cycle counter and a count of the event counter.