- Patent Title: Semiconductor memory device for resetting counter synchronized with data clock by using reset signal synchronized with system clock and method for operating the same
-
Application No.: US16128803Application Date: 2018-09-12
-
Publication No.: US10861515B2Publication Date: 2020-12-08
- Inventor: Kang-Sub Kwak , Sang-Sic Yoon , Young-Jun Yoon
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2018-0040550 20180406
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C11/34 ; G11C7/10
Abstract:
An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.
Public/Granted literature
- US20190311752A1 SEMICONDUCTOR MEMORY DEVICE AND THE METHOD FOR OPERATING THE SAME Public/Granted day:2019-10-10
Information query
