A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.