Memory device provided with a set of memory cells having a first inverter and a second inverter each connected to a supply line from a first supply line and a second supply line, the memory device being provided with a circuit element configured for: during a start-up phase consecutive to a powering on, applying a first pair of potentials, respectively to the first supply line and the second supply line, in order to pre-load a logic data to some cells depending on the manner in which said cells are respectively connected to said supply lines, then during a second phase, applying a second pair of potentials respectively to said first supply line and the second supply line, so as to symmetrically supply the inverters of each cell.