Invention Grant
- Patent Title: Pattern fidelity enhancement
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Application No.: US15689172Application Date: 2017-08-29
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Publication No.: US10861698B2Publication Date: 2020-12-08
- Inventor: Yu-Tien Shen , Ya-Wen Yeh , Wei-Liang Lin , Ya Hui Chang , Yung-Sung Yen , Wei-Hao Wu , Li-Te Lin , Ru-Gun Liu , Kuei-Shun Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/027
- IPC: H01L21/027 ; H01L21/033 ; G03F7/09 ; H01L21/311 ; H01L21/306 ; G03F7/20 ; G03F7/11

Abstract:
The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate, wherein the substrate includes a plurality of features to receive a treatment process; forming at least one opening in the patterning layer, wherein the plurality of features is partially exposed in the at least one opening; applying a directional etching to expand the at least one opening in a first direction, thereby forming at least one expanded opening; and performing the treatment process to the plurality of features through the at least one expanded opening.
Public/Granted literature
- US20190067000A1 Pattern Fidelity Enhancement Public/Granted day:2019-02-28
Information query
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