Invention Grant
- Patent Title: Method of forming trenches with different depths
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Application No.: US16403921Application Date: 2019-05-06
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Publication No.: US10861740B2Publication Date: 2020-12-08
- Inventor: Chao-Hsun Wang , Hsien-Cheng Wang , Mei-Yun Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/485
- IPC: H01L23/485 ; H01L21/768 ; H01L21/311 ; H01L29/43 ; H01L29/08 ; H01L21/8234 ; H01L29/40

Abstract:
A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.
Public/Granted literature
- US20190259657A1 Method of Forming Trenches with Different Depths Public/Granted day:2019-08-22
Information query
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