A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.