Invention Grant
- Patent Title: Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET
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Application No.: US16599912Application Date: 2019-10-11
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Publication No.: US10861749B2Publication Date: 2020-12-08
- Inventor: Yen-Ting Chen , Wei-Yang Lee , Feng-Cheng Yang , Yen-Ming Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/8238 ; H01L21/02 ; H01L27/092 ; H01L21/311 ; H01L29/08 ; H01L29/161

Abstract:
A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure and over the first layer. The gate layer is patterned into a gate stack that wraps around the fin structure. A second layer is formed over the first layer and over the gate stack. A first etching process is performed to remove portions of the second layer formed over the fin structure, the first layer serves as an etching-stop layer during the first etching process. A second etching process is performed to remove portions of the first layer to expose a portion of the fin structure. A removal of the portions of the first layer does not substantially affect the second layer. A source/drain region is epitaxially grown on the exposed portion of the fin structure.
Public/Granted literature
- US20200043804A1 Using a Metal-Containing Layer as an Etching Stop Layer and to Pattern Source/Drain Regions of a FinFET Public/Granted day:2020-02-06
Information query
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