Invention Grant
- Patent Title: Method of semiconductor integrated circuit fabrication
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Application No.: US16687152Application Date: 2019-11-18
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Publication No.: US10861751B2Publication Date: 2020-12-08
- Inventor: De-Wei Yu , Chia Ping Lo , Liang-Gi Yao , Weng Chang , Yee-Chia Yeo , Ziwei Fang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/8234 ; H01L21/02 ; H01L21/268 ; H01L21/324 ; H01L29/66
Abstract:
A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.
Public/Granted literature
- US20200083112A1 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION Public/Granted day:2020-03-12
Information query
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