Invention Grant
- Patent Title: Dummy die placement without backside chipping
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Application No.: US16415009Application Date: 2019-05-17
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Publication No.: US10861799B1Publication Date: 2020-12-08
- Inventor: Chih-Wei Wu , Li-Chung Kuo , Pu Wang , Ying-Ching Shih , Szu-Wei Lu , Kung-Chen Yeh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/3105
- IPC: H01L21/3105 ; H01L21/48 ; H01L21/56 ; H01L21/78 ; H01L23/00 ; H01L23/31 ; H01L23/498 ; H01L25/00 ; H01L25/18
Abstract:
A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.
Public/Granted literature
- US20200365525A1 Dummy Die Placement Without Backside Chipping Public/Granted day:2020-11-19
Information query
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