Invention Grant
- Patent Title: Semiconductor chip stack and method for manufacturing semiconductor chip stack
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Application No.: US16422580Application Date: 2019-05-24
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Publication No.: US10861813B2Publication Date: 2020-12-08
- Inventor: Toshiya Ishio
- Applicant: SHARP KABUSHIKI KAISHA
- Applicant Address: JP Sakai
- Assignee: SHARP KABUSHIKI KAISHA
- Current Assignee: SHARP KABUSHIKI KAISHA
- Current Assignee Address: JP Sakai
- Agency: ScienBiziP, P.C.
- Priority: JP2018-103563 20180530
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction.
Public/Granted literature
- US20190371756A1 SEMICONDUCTOR CHIP STACK AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP STACK Public/Granted day:2019-12-05
Information query
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