Invention Grant
- Patent Title: Electronic device and manufacturing method therefor
-
Application No.: US16166201Application Date: 2018-10-22
-
Publication No.: US10861880B2Publication Date: 2020-12-08
- Inventor: Keisuke Harada
- Applicant: Japan Display Inc.
- Applicant Address: JP Minato-ku
- Assignee: Japan Display Inc.
- Current Assignee: Japan Display Inc.
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2017-208380 20171027
- Main IPC: H01L27/12
- IPC: H01L27/12

Abstract:
An electronic device has a multilayer structure including a plurality of wires in multiple layers, and a conductive material on a surface of the multilayer structure for electrically connecting two or more wires included in the plurality of wires. The surface of the multilayer structure has a first recess. The conductive material is in the first recess and on the surface of the multilayer structure. The conductive material has an upper surface. The upper surface has a second recess corresponding to the first recess. The second recess has a bottom surface at a higher position than an upper surface of the uppermost layer of the two or more wires.
Public/Granted literature
- US20190131319A1 ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREFOR Public/Granted day:2019-05-02
Information query
IPC分类: