Invention Grant
- Patent Title: Array substrate
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Application No.: US16230191Application Date: 2018-12-21
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Publication No.: US10861881B2Publication Date: 2020-12-08
- Inventor: Ching Fu Chien
- Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Applicant Address: CN Guangdong
- Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee Address: CN Guangdong
- Agent Leong C. Lei
- Priority: CN201810810917 20180720
- Main IPC: H04L27/12
- IPC: H04L27/12 ; H01L27/12 ; H01L27/32 ; G09G3/3266 ; H01L51/44 ; G09G3/3275

Abstract:
The array substrate taught by the present invention have dummy ITO lines on the fanout lines configured as multiple segments separated at intervals so that, when two neighboring dummy ITO lines are short-circuited, the place of short circuit is limited to a segment of the neighboring dummy ITO lines. Coupling capacitance is limited to that between the segments and fanout lines. Compared to prior arts where coupling capacitance occurs between neighboring dummy ITO lines and fanout lines, the present invention has much smaller coupling capacitance, thereby reducing the impact of coupling capacitance to signal transmission on the fanout lines, avoiding the occurrence of light lines on the display panel, and enhancing the display effect of the display panel.
Public/Granted literature
- US20200027902A1 ARRAY SUBSTRATE Public/Granted day:2020-01-23
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