Invention Grant
- Patent Title: Interconnect structure for stacked device and method
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Application No.: US16723467Application Date: 2019-12-20
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Publication No.: US10861899B2Publication Date: 2020-12-08
- Inventor: Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung , Tzu-Hsuan Hsu , Shu-Ting Tsai , Min-Feng Kao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L27/146 ; H01L21/768 ; H01L23/48

Abstract:
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
Public/Granted literature
- US20200127027A1 Interconnect Structure for Stacked Device and Method Public/Granted day:2020-04-23
Information query
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