Invention Grant
- Patent Title: Semiconductor device source/drain region with arsenic-containing barrier region
-
Application No.: US16531421Application Date: 2019-08-05
-
Publication No.: US10861935B2Publication Date: 2020-12-08
- Inventor: Chien-I Kuo , Shao-Fu Fu , Chia-Ling Chan , Yi-Fang Pai , Li-Li Su , Wei Hao Lu , Wei Te Chiang , Chii-Horng Li
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/167 ; H01L29/36 ; H01L21/223 ; H01L21/02 ; H01L29/78 ; H01L29/66 ; H01L21/22 ; H01L21/3065 ; H01L21/306

Abstract:
The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
Public/Granted literature
- US20190355816A1 Semiconductor Device Source/Drain Region with Arsenic-Containing Barrier Region Public/Granted day:2019-11-21
Information query
IPC分类: