Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.