Invention Grant
- Patent Title: Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage
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Application No.: US16390373Application Date: 2019-04-22
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Publication No.: US10861972B2Publication Date: 2020-12-08
- Inventor: Zhiqiang Wu , Yi-Ming Sheu , Tzer-Min Shen , Chun-Fu Cheng , Hong-Shen Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/08 ; H01L29/06 ; H01L29/66 ; H01L29/10 ; H01L21/265

Abstract:
The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.
Public/Granted literature
- US20190245089A1 CHANNEL STRAIN INDUCING ARCHITECTURE AND DOPING TECHNIQUE AT REPLACEMENT POLY GATE (RPG) STAGE Public/Granted day:2019-08-08
Information query
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