Invention Grant
- Patent Title: Nano power under-voltage lockout circuits (UVLO) using flipped-gate MOS
-
Application No.: US15727775Application Date: 2017-10-09
-
Publication No.: US10862469B2Publication Date: 2020-12-08
- Inventor: Daisuke Kobayashi , Soichiro Ohyama
- Applicant: Dialog Semiconductor (UK) Limited
- Applicant Address: GB London
- Assignee: Dialog Semiconductor (UK) Limited
- Current Assignee: Dialog Semiconductor (UK) Limited
- Current Assignee Address: GB London
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Billy Knowles
- Main IPC: H02H3/24
- IPC: H02H3/24 ; H03K5/24 ; H02H1/00 ; H02H9/00 ; H02H7/00

Abstract:
An under-voltage lockout (UVLO) circuit configured for indicating that an electronic device may be enabled and disabled based on threshold levels of a power supply voltage. The UVLO circuit has a non-differential comparator configured to have a fixed threshold voltage. A voltage divider having a first terminal connected to the power supply voltage and configured to adapt a compare signal applied to the non-differential comparator to be proportional the power supply voltage such that a desired threshold voltage for the power supply voltage causes the non-differential comparator to change its output state. The UVLO circuit has a hysteresis controller configured for adjusting the compare voltage such that the power supply voltage has at least two threshold voltages to cause the non-differential comparator to change states. The non-differential comparator comprises a flipped gate transistor with a gate-to-source threshold greater than a normally gated transistor.
Public/Granted literature
- US20190109589A1 Nano Power Under-Voltage Lockout Circuits (UVLO) Using Flipped-Gate MOS Public/Granted day:2019-04-11
Information query