Disclosed herein are switching or other active field-effect transistor (FET) configurations that implement independently controlled main-auxiliary branch designs. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FET devices in parallel with a plurality of auxiliary FET devices. The circuit assembly can include a plurality of gate bias networks where each controls one or more of the main FET devices. The circuit assembly includes a second plurality of gate bias networks that each controls one or more of the auxiliary FET devices.