Invention Grant
- Patent Title: Clearance size reduction for backdrilled differential vias
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Application No.: US16655621Application Date: 2019-10-17
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Publication No.: US10863628B2Publication Date: 2020-12-08
- Inventor: Matthew Twarog , Hui He , Thomas W. Jetton
- Applicant: Juniper Networks, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Juniper Networks, Inc.
- Current Assignee: Juniper Networks, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Harrity & Harrity, LLP
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/02 ; H05K3/00 ; H05K3/46 ; H05K3/40 ; H05K3/22

Abstract:
A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
Public/Granted literature
- US20200053880A1 CLEARANCE SIZE REDUCTION FOR BACKDRILLED DIFFERENTIAL VIAS Public/Granted day:2020-02-13
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