Invention Grant
- Patent Title: Test of stacked transistors
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Application No.: US15188788Application Date: 2016-06-21
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Publication No.: US10884050B2Publication Date: 2021-01-05
- Inventor: Eric S. Shapiro
- Applicant: pSemi Corporation
- Applicant Address: US CA San Diego
- Assignee: pSemi Corporation
- Current Assignee: pSemi Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jaquez Land Greenhaus LLP
- Agent Alessandro Steinfl, Esq.
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H03K19/0175 ; H03K19/20 ; H03K19/21 ; H01L27/12

Abstract:
A stack of series coupled transistors comprising, at least two sub-portions of the stack of series coupled transistors, and at least one logic decoder coupled to the at least two sub-portions to turn ON at least one sub-portion.
Public/Granted literature
- US20170363676A1 Design for Test of Stacked Transistors Public/Granted day:2017-12-21
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