A clock glitch detection circuit includes a detection circuit and a logic circuit. The detection circuit is configured to receive a clock input signal and a clock output signal and determines whether the clock input signal and the clock output signal are in phase, so as to output a first detection signal and a second detection signal. The logic circuit is coupled to the detection circuit and configured to receive the first detection signal and the second detection signal. The logic circuit determines whether the first detection signal and the second detection signal are in phase, so as to generate a glitch detection signal. The glitch detection signal is configured to indicate whether clock glitch occurs in the clock input signal.