Invention Grant
- Patent Title: Fault tolerant memory system
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Application No.: US16043975Application Date: 2018-07-24
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Publication No.: US10884850B2Publication Date: 2021-01-05
- Inventor: Reiley Jeyapaul , Roxana Rusitoru , Jonathan Curtis Beard
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Leveque IP Law, P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; G06F3/06 ; G06F11/20 ; G06F12/02 ; G11C29/00

Abstract:
A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.
Public/Granted literature
- US20200034230A1 FAULT TOLERANT MEMORY SYSTEM Public/Granted day:2020-01-30
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