Invention Grant
- Patent Title: Resiliency to memory failures in computer systems
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Application No.: US16385448Application Date: 2019-04-16
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Publication No.: US10884859B2Publication Date: 2021-01-05
- Inventor: Laurence S. Kaplan , Preston Pengra Briggs, III , Miles Arthur Ohlrich , Willard Huston Leslie
- Applicant: Cray Inc.
- Applicant Address: US WA Seattle
- Assignee: Cray Inc.
- Current Assignee: Cray Inc.
- Current Assignee Address: US WA Seattle
- Agency: Hewlett Packard Enterprise Patent Department
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F11/14 ; G06F11/20 ; G06F3/06 ; G06F11/16 ; G06F11/08

Abstract:
A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
Public/Granted literature
- US20190243710A1 RESILIENCY TO MEMORY FAILURES IN COMPUTER SYSTEMS Public/Granted day:2019-08-08
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