Invention Grant
- Patent Title: Speculative checkin of ERAT cache entries
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Application No.: US16117099Application Date: 2018-08-30
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Publication No.: US10884943B2Publication Date: 2021-01-05
- Inventor: Bartholomew Blaner , Jay G. Heaslip , Robert D. Herzl , Jody B. Joyner , Jeffrey A. Stuecheli
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F12/0897 ; G06F12/1009

Abstract:
A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes setting a threshold number of free Effective to Real Address Translation (ERAT) cache entries in an ERAT cache; determining whether a total number of free ERAT cache entries is less than or equal to the threshold number of free ERAT cache entries; allocating, in response to determining that the total number of free entries is less than or equal to the threshold number, one or more active ERAT cache entries to be speculatively checked in to a memory management unit (MMU); and speculatively checking in the one or more active ERAT cache entries to the MMU.
Public/Granted literature
- US20200073816A1 SPECULATIVE CHECKIN OF ERAT CACHE ENTRIES Public/Granted day:2020-03-05
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