Invention Grant
- Patent Title: Method and apparatus to manage flush of an atomic group of writes to persistent memory in response to an unexpected power loss
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Application No.: US16012515Application Date: 2018-06-19
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Publication No.: US10885004B2Publication Date: 2021-01-05
- Inventor: Karthik Kumar , Francesc Guim Bernat , Thomas Willhalm , Mark A. Schmisseur , Benjamin Graniello
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law, PC
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F16/22 ; G06F12/02 ; G06F11/14 ; G06F12/0804 ; G06F16/27
Abstract:
A group of cache lines in cache may be identified as cache lines not to be flushed to persistent memory until all cache line writes for the group of cache lines have been completed.
Public/Granted literature
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